PinPort
Application: Post-Silicon Verification
The
Challenge
You are
using an FPGA for a large portion of the functionality of a system
you are developing. There are several other smaller packaged
parts combined with the FPGA. Together, these will be interconnected
on a printed circuit board (PCB), which is not yet available.
You have
written the RTL for the FPGA. The extensive set of test case
you have developed and run on the simulator show that the FPGA
is functioning the way you intend. You have synthesized the RTL
into gates. Laying out the gate level netlist has given you everything
you need to program the FPGA. It has also provided an SDF file
which can be used with the gate level netlist for timing simulations.
What do
you do next?
Do you
run your extensive simulation suite for the FPGA against the
gate level netlist annotated with delay information from the
SDF file? These simulations would give you added confidence that
synthesis and layout have not affected the intended design. However,
since the simulations took a long time at the RTL level, you
can't justify the time that this would take for the extra confidence
it would give you.
Do you
design and manufacture the PCB? This takes some time and if things
are not right you need to respin the board. Alternatively, you
could breadboard the entire system. In both these cases you are
forced to debug system problems with test equipment, not the
logic simulators's interactive debugging environment with which
you have become very productive. You would really like to use
the logic simulator and do timing simulations of the entire system.
Since you have simulation timing models for all the parts on
the PCB and a simulatable representation of the FPGA, model availability
is not an issue. Further, you can get some estimates of the trace
delays from early work you have done with your PCB design tool.
The real problem is simulation performance. It would just take
too long
The
Approach
By using
PinPort, the suite of simulation test cases for the FPGA can
be efficiently run against the programmed FPGA, verifying its
operation prior to its incorporation into the system. Further,
the programmed FPGA can be used in the timing simulations of
the full system, allowing them to complete in a reasonable about
of time.
Prepare
the FPGA
After
synthesizing and laying out the FPGA, proceed to programming
it. The programmed FPGA is mounted on an adapter board and inserted
into a PinPort device. The PinPort device is connected to a workstation
through a SCSI interface. Your Verilog logic simulator running
on the workstation communicates with the FPGA through the PinPort
programming interface (a collection of Verilog PLI calls). There
is a Verilog wrapper module for the FPGA which presents its pin
interface. The wrapper module communicates signal changes between
the simulation and the FPGA by making PLI calls.
Verify
the Programmed FPGA
The first
simulation step is to run the test cases against the programmed
FPGA. This verifies that nothing unexpected was introduced during
synthesis and layout. All that is required is to replace in the
testbench the instance of the top-level module for the FPGA with
that for the Verilog wrapper module. Now when the test cases
are run, the internal delays within the FPGA are those of the
actual part. Because the simulator does not need to compute the
detailed behavior of the FPGA, but only prepare its inputs and
capture its outputs, the entire suite of test cases runs very
quickly. If there is any unexpected behavior, you investigate
it using the interactive debug capabilities of the simulator.
Add
Timing
Though
the internal timing of the FPGA is that of the actual part, the
timing of the signals at the pins of the FPGA is not yet accounted
for. The wrapper module is extended to incorporate it. These
extensions take the form of propagation delays on inputs, outputs,
and/or between pins. If you want to automatically check that
timing conditions are satisfied, you can add setup, hold, and
pulse width checks.
You now
have timing models for all parts in the system. What is missing
is an estimate of the trace delays that will exist at the PCB
level. Fortunately, you have done enough early work on the design
of the PCB that your design tool can output an SDF file containing
these estimates. You use this file during your system simulations.
Simulate
the System
You run
your system simulations with full timing. Your simulator allows
you to run with minimum and maximum delay times, in addition
to typical ones. The timing checks that you built into the Verilog
wrapper module, detect some timing violations. After examining
the waveforms you determine these are due to large delays on
some of the input signals to the FPGA. You use this information
to modify the routing of these traces. When you rerun the simulations
with the revised delay estimates, the timing violations are eliminated.
Throughout all the simulation runs you are pleased with how quickly
the full timing simulations run. You attribute this to the speed
with which the FPGA is evaluated during simulation.
The
Result
This application
of PinPort allows you to use the full interactive debugging capabilities
of your logic simulator to verify the progammed FPGA, as well
as the entire system. PinPort saves the logic simulator from
having to evaluate the detailed behavior of the FPGA, making
full timing simulation of the FPGA in the entire system practical.
The end result is that the system is verified, both for functionality
and timing, before the PCB is completely designed and built. |
